There exist integrated circuits comprising:
a) an on-chip memory data bus having a plurality of conductive wires to communicate data stored in a memory to at least one device,
b) an on-chip memory connected to the memory data bus, the on-chip memory being controllable to set either a logical one or a logical zero on each of the wires of the memory data bus according to data stored in a memory segment, so that the data stored in the memory segment can be communicated to at least one peripheral device in response to a read instruction,
c) an on-chip access right manager to grant or deny access to the memory segment to the peripheral device according to predetermined access rights upon reception of a read instruction from the peripheral device.
The on-chip memory data bus is directly connected to the peripheral devices. During the operation of the integrated circuit, the access right manager assesses the access rights of each peripheral device that sends a read instruction concerning data stored in the memory segment.
If the peripheral device has a right to access the memory segment, the access right manager grants the access and only then is the on-chip memory controlled to communicate the stored data to the device over the memory data bus.
The operation of assessing the access right of the device and controlling the memory to communicate the stored data take time and slow down the data communication speed between the on-chip memory and the peripheral device.
An example of a memory, access to which is assessed by an access right manager is given in patent application US 2003/0041254 to Challener et al.